Anonymous Gerbil

I decided to dump this one in here as there wasn't any other Science & Tech topic, and this is much science and technology (if old) as anything.

This is about clocks, and building one. Why would I build something that I can buy new for $5 or less? I'm not talking about building one these....
I'm talking about building one of these....
Or one of these...
Or something in between. This is a combination of a study in how discrete logic works, and of art.

This thread will be something of an engineering notebook for the project. If things go well, it will also be a build log.

I've got a Heathkit (yes, they still exist) clock kit I need to build. It'll replace the Heathkit clock that replaced the Heathkit clock.

What do you need to make a clock? Counters. You have to be able to count the passage of time some how. For those who aren't deep into the digital logic that makes up computers, one of the most common counter elements is the D flip flop.
When the clock signal pulses, the logic value present on the D input is stored and output on the Q output. The ~Q (not Q) output is always the opposite of the Q output. If you connect the ~Q output back to D, you get something that divides the clock by two. By feeding the Q output to the clock input of the next stage, you can create an arbitrary length binary counter.
I'll leave it up to those that are interested to go look up the discrete logic circuits for a D, and edge triggered D flip flop. I'm looking at making a clock out f discrete transistors, and not ICs. So what does it take to make a D flip flop out of transistors. Well, it depends. If you mirror what you would get in a 7474 TTL chip (dual D flip flop), then it looks something like this.

That's a lot of transistors, especially considering it takes four D flip flops to count to 10. Here's the thing. In integrated circuits, resistors and transistor are "cheap". Other passives, like capacitors and inductors are "expensive". It's hard to make a high value capacitor on a tiny hunk of silicon. But, when you move into the discrete world, capacitors are much easier. If you are willing to forgot the strict RTL (Resistor Transistor Logic) and entertain other passive components, you can get the same counting capability out of this circuit.
It you go digging online, lots of people call this a "T flip-flop", where T is for Toggle. It has the exact same behavior as a D flip-flop with ~Q looped back to D. The output toggles for each clock pulse. This is actually a S/R (Set/Reset) flip-flop with some pulse steering. Note, this toggles on pulses, not edges.

So, what are we counting? Well, the most common thing is AC frequency -- 60Hz here, 50Hz in many other parts of the world, 400Hz on an airplane (internal power systems, not your seat outlet). As an aside, and aircraft seat power outlet can be either 50Hz or 60Hz depending on the country, but will be 115VAC. Anyway, back to counting things. Clocks count seconds, so if we use the AC line frequency as the reference, we need to divide it by 60 (sticking with the US here) to get one count per second. To do so, with a binary counter, you need 6 stages and some logic so that when the counter output is 111100, it resets to 0.

There is a bit of forethought needed here though. How to do you set a clock? Most cheap digital clock have a set button and the an hour and minute button that increment the respective counts. Others have a fast and slow set button that increment the count automatically while they are held. The slow button will usually increment the minutes once per second and the fast at something significantly faster, maybe ten times a second. To do that you would need a 10Hz pulse for the fast increment and the standard 1Hz for the slow. Turns out that isn't so bad to generate and only costs you one extra flip flop stage. First you divide by 6 (three flip flops) to get 10Hz, then you divide by 10 (four flip flops) to get 1Hz. What does it look like?

This. This counter structure is relatively obvious. The small sections of circuit at the bottom take the square waves present on the CLK_10HZ and CLK_1HZ lines and generate pulses on the falling edge. The above circuit does actually simulate. The waveforms, starting with the CLK_10HZ signal, look something like this.

If you are using the AC power frequency for your timing, you can't use one of the current, efficient wall-wart switching power supplies. They provide clean, DC power. Instead, you have to go back and use a transformer. I would probably use a 12VAC wall wart transformer, rather than putting the transformer in the actual clock, both for size and aesthetics.

Behold, as 12V regulated supply, with a 60Hz clock output.
To be fair, its actually 11.6V, but close enough. Nothing in this clock would be particularly sensitive to the actual voltage. The important part is to keep the DC power clean as you don't want excessive ripply messing up your counting circuits. A fully digital design would not be super sensitive to ripple, so long as the long levels were ok. However, when you have capacitors doing your pulse steering, AC ripple in the power can have weird side effects.

D1-D4 are a bridge rectifier and C2 is the bulk smoothing cap. It was sized so that the regulator would stay within regular at approximately 1A of current draw. Higher load and the capacitor would need to increase in size appropriately. R3 and D5 create a voltage reference that sets the regulated output voltage. The zener diode, D5 is a 13V diode. The Q2 and Q3 will drop the output voltage by 1.4V, but I didn't have a 13.4V diode with a spice model readily available. Q2/Q3 are wired as a darlington pair with Q3 being the regulator pass transistor. I am hoping that the full design won't need a full amp as Q2 would be dissipating nearly 2W at that point. Rl is just to simulate the load of the system.

The tap that leads to R2/R4 pulls a 60Hz half wave signal that drives Q1 to generate a square wave output for a 60Hz clock. Q1 turns starts to turn off as soon as the AC voltage rises about about 300mV and is full off by 700mV. This is reversed on the falling side of the AC cycle. The result is a reasonably square wave form with approx 60us rise/fall time.

The above counters are binary and make sense in the context of computers and things that need to do binary operations. There are other ways to count. Below is a ring counter. At any given time, one stage of the counter is active and it steps along till it hits the end and loops around, hence the "ring" name.
The above is actually a divide-by-60 counter. It's made up of a 6 stage ring feeding a 10 stage ring. Below are traces from each stage of the 6 stage ring. You can see the active pulse work its way across the counter.
Each stage of the ring is made up of a complementary pair of transistors. Wired the way they are, they simulate an SCR. In fact, you can make a ring counter out of SCRs, if so desired, or if you want to switch higher voltages. One of the interesting things about this ring counter design is that you can replace the diode with and LED and the display is built into the counter. So, you can actually change two 60 stage ring counters, followed by a 12 stage counter and have a complete clock for ~280 transistors.

A new project! Nice.

But why keep it hidden here? You should start a public blog, or write in an established site.
Or maybe under www.anonymousgerbil.com? (That's a mouthful, though.)

meerkt wrote: ↑Thu Feb 25, 2021 7:31 am A new project! Nice.

But why keep it hidden here? You should start a public blog, or write in an established site.
Or maybe under www.anonymousgerbil.com? (That's a mouthful, though.)

Mainly because I can do a running log here and then if I want to take the time and effort to make a real article about it, I can. Takes a lot of time and effort to do writing and in a more public forum, there become expectations of continuing progress (even if they are self imposed), which turns it in work rather than play.

--SS

If I am doing both digital and analog (LED rings) then using 60 stage ring counters gets a bit complex, though it would be doable. Each digit would need a decimal to 7-segment decoder, with each decimal input having a 6 input for connection to the appropriate ring counter stages. BCD to 7-seg decoders are actually pretty complex beasts.
You can find various implementations, but logically they are all equivalent and would all require at least 36 transistors to drive. Further, I would need a BCD to decimal decoder which would be at least 42 transistors. That assumes all the gates implemented as DTL logic. Each gate would need a transistor for the negative version of the logic (NOR, NAND) and then an inverter following it. So let's see... 34 transistors for the digit counters, plus 78 for display decoding is 112 total. That might actually be more efficient. Going into this post I was discounting the BCD option as too high a transistor count. However, it might be the most efficient option. Will have to investigate further.

Back to ring counting...

One thing I have been debating is whether to do three LED rings, hour, minute, and second, or one ring of RGB LEDs that has hours, minutes, and seconds as different colors. One of the downsides to the RGB is that you get them as either common cathode or common anode. Because the pulse line of the ring counter connects to the cathode, a common cathode setup would clock all three counters (hr, min, sec) at the same time. So, to use RGB, we have to pull the LEDs out of the counters and drive them from the counter outputs via a drive transistor. That adds at least one transistor per counter stage.

In reality that extra drive transistor per stage is needed regardless, as it would be needed to drive the decimal to 7-seg decoder. If I go with one ring counter per clock digit, it keeps down the transistor count due to the ring counters, approx 400 for 12+60+60 stage counters versus about 100 for 2+3+6+10+6+10 stage counters. The trade off is that we then need to decode the counter outputs to drive 60 LEDs, whether RGB or individual. I'll need to look at how many transistors are needed for that. The simple decode method would need two transistors per LED for 264 transistors plus the 100 for counting, which is still less than the 400 needed for direct drive. I might be able to cut that down with multiplexing of some sort.

One thing I know I need for a ring counter is a decimal to 7-seg decoder. Because only one input is active to select the display digit, it is much simpler than a BCD decoder and can be implemented as a diode array with drive transistors.
Here is the waveform of the decoder in operation. Note that the inputs are actually being toggled in what looks like a weird way. That is a multiplexing clock that I was testing. I left it in because it makes it much easier to identify the segment states than just the normal high/low signal state.
One interesting thing to note about this simulation is that at the start, both stage 1 and stage 8 are active. After the first clock tick, the counter corrects itself and starts counting properly. The actual circuit will start in some indeterminate state and when powered up, it will start counting from a random count. The Spice simulation actually emulates this properly. It happens to start counting a 2 in this simulation, but the starting point varies in each simulation run.

--SS